• Channel and Pin Assignment for Three Dimensional Packaging Routing 

      Minz, Jacob Rajkumar; Lim, Sung Kyu (Georgia Institute of Technology, 2004-05-24)
      Three dimensional packaging is becoming a popular concept because of the numerous advantages it has to offer over the existing conventional technologies. System on Packages (SOP) is an example of three dimensional packaging. ...
    • Congestion and Power Integrity Aware Placement and Routing for 3D Packaging 

      Minz, Jacob Rajkumar; Choi, Jinwoo; Swaminathan, Madhavan; Lim, Sung Kyu (Georgia Institute of Technology, 2004-04-23)
      One of the major concerns for a 3-D package is to deal with power supply noise. Decoupling Capacitances (decap) allocation is a powerful technique to suppress power supply noise. In this work we integrate noise analysis ...
    • Multi-layer Floorplanning for Reliable System-on-Package 

      Shiu, Pun Hang; Lim, Sung Kyu (Georgia Institute of Technology, 2003)
      Physical design automation for the new emerging mixed-signal System-on-Package (SOP) technology requires a new kind of floorplanner--it must place both active components such as digital IC, analog ICs, memory modules, MEMS, ...
    • Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design 

      Ekpanyapong, Mongkol; Minz, Jacob Rajkumar; Watewai, Thaisiri; Lee, Hsien-Hsin Sean; Lim, Sung Kyu (Georgia Institute of Technology, 2003)
      As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communication within a single cycle, thus decaying ...
    • Simultaneous Delay and Power Optimization for Multi-level Partitioning and Floorplanning with Retiming 

      Ekpanyapong, Mongkol; Lim, Sung Kyu (Georgia Institute of Technology, 2003)
      Delay minimization and power minimization are two important objectives in the design of the high-performance, portable, and wireless computing and communication systems. Retiming is a very effective way for delay optimization ...
    • Thermal-aware 3D Microarchitectural Floorplanning 

      Ekpanyapong, Mongkol; Healy, Michael; Ballapuram, Chinnakrishnan S.; Lim, Sung Kyu; Lee, Hsien-Hsin Sean; Loh, Gabriel H. (Georgia Institute of Technology, 2004)
      Next generation deep submicron processor design will need to take into consideration many performance limiting factors. Flip flops are inserted in order to prevent global wire delay from becoming nonlinear, enabling deeper ...
    • Thermal-driven Circuit Partitioning and Floorplanning with Power Optimization 

      Lee, Kyoung-Keun; Paradise, Edward J.; Lim, Sung Kyu (Georgia Institute of Technology, 2003)
      In this paper, we present methodology to distribute the temperature of gates evenly on a chip while simultaneously reducing the power consumption by using newly designed partitioning and floorplanning algorithms. This new ...