Now showing items 1-20 of 23

    • Analysis of a Redactable Signature Scheme on Data With Dependencies 

      Bauer, David; Blough, Douglas M. (Georgia Institute of Technology, 2009)
      Storage of personal information by service providers risks privacy loss from data breaches. Our prior work on minimal disclosure credentials presented a mechanism to limit the amount of personal information provided. ...
    • Centralized Buffer Router with Elastic Links and Bubble Flow Control 

      Hassan, Syed Minhaj; Yalamanchili, Sudhakar (Georgia Institute of Technology, 2013)
      While router buffers have been used as performance multipliers, they are also major consumers of area and power in on-chip networks. In this paper, we propose centralized elastic bubble router - a router micro-architecture ...
    • Chameleon: Virtualizing Idle Acceleration Cores of A Heterogeneous Multi-Core Processor for Caching and Prefetching 

      Woo, Dong Hyuk; Fryman, Joshua B.; Knies, Allan D.; Lee, Hsien-Hsin Sean (Georgia Institute of Technology, 2008)
      Heterogeneous multi-core processors have emerged as an energy- and area-efficient architectural solution to improving performance for domain-specific applications such as those with a plethora of data-level parallelism. These ...
    • A Characterization and Analysis of GPGPU Kernels 

      Kerr, Andrew; Diamos, Gregory; Yalamanchili, Sudhakar (Georgia Institute of Technology, 2009-05-05)
      General purpose application development for GPUs (GPGPU) has recently gained momentum as a cost-effective approach for accelerating data- and compute-intensive applications, pushed to the forefront by the introduction of ...
    • The Design and Implementation Ocelot’s Dynamic Binary Translator from PTX to Multi-Core x86 

      Diamos, Gregory (Georgia Institute of Technology, 2009)
      Ocelot is a dynamic compilation framework designed to map the explicitly parallel PTX execution model used by NVIDIA CUDA applications onto diverse many-core architectures. Ocelot includes a dynamic binary translator ...
    • Design Space Exploration of On-chip Ring Interconnection for a CPU-GPU Architecture 

      Lee, Jaekyu; Li, Si; Kim, Hyesoon; Yalamanchili, Sudhakar (Georgia Institute of Technology, 2012)
      Future chip multiprocessors (CMP) will only grow in core count and diversity in terms of frequency, power consumption, and resource distribution. Incorporating a GPU architecture into CMP, which is more efficient with ...
    • Dominant Variance Characterization 

      Kumar, Tushar; Pande, Santosh (Georgia Institute of Technology, 2010)
      There are a whole range of program analysis techniques that characterize different aspects of an application’s performance: hot-spots, distinct phases of behavior, code segments that could potentially run in parallel, ...
    • A Dynamic, Partitioned Global Address Space Model for High Performance Clusters 

      Yalamanchili, Sudhakar; Young, Jeff; Duato, José; Silla, Federico (Georgia Institute of Technology, 2008)
      Memory-to-memory latency is a critical performance determinant of scalable computing systems. The use of modern interconnect fabrics tightly coupled to the processor-memory hierarchy such as AMD’s HyperTransportTM (HT) ...
    • Energy Introspector: Coordinated Architecture-Level Simulation of Processor Physics 

      Song, William J.; Mukhopadhyay, Saibal; Rodrigues, Arun; Yalamanchili, Sudhakar (Georgia Institute of Technology, 2013)
      Increased power and heat dissipation in microprocessors impose limitations on performance scaling. Power and thermal management techniques coupled with workload dynamics cause increasing spatiotemporal variations in ...
    • Execution Environment Support for Many Core Heterogeneous Accelerator Platforms 

      Gupta, Vishakha; Yalamanchili, Sudhakar; Duato, José (Georgia Institute of Technology, 2010)
      We are seeing the advent of large scale, heterogeneous systems comprised of homogeneous general purpose cores intermingled with customized heterogeneous cores and interconnected to diverse memory hierarchies. The presence ...
    • Fast and Accurate Link Discovery Integrated with Reliable Multicast in 802.11 

      Lertpratchya, Daniel; Blough, Douglas M.; Riley, George F. (Georgia Institute of Technology, 2013)
      Abstract—Maintaining accurate neighbor information in wireless networks is an important operation upon which many higher layer protocols rely. However, this operation is not supported in the IEEE 802.11 MAC layer, ...
    • A HyperTransport-Enabled Global Memory Model For Improved Memory Efficiency 

      Young, Jeffrey; Yalamanchili, Sudhakar; Silla, Federico; Duato, José (Georgia Institute of Technology, 2008)
      Modern and emerging data centers are presenting unprecedented demands in terms of cost and energy consumption, far outpacing architectural advances related to economies of scale. Consequently, blade designs exhibit ...
    • A New Temperature Distribution Measurement Method on GPU Architectures Using Thermocouples 

      Dasgupta, Aniruddha; Hong, Sunpyo; Kim, Hyesoon; Park, Jinil (Georgia Institute of Technology, 2012)
      In recent years, the many-core architecture has seen a rapid increase in the number of on-chip cores with a much slower increase in die area. This has led to very high power densities in the chip. Hence, in addition to ...
    • A Patient-centric, Attribute-based, Source-verifiable Framework for Health Record Sharing 

      Mohan, Apurva; Bauer, David; Blough, Douglas M.; Ahamad, Mustaque; Bamba, Bhuvan; Krishnan, Ramkumar; Liu, Ling; Mashima, Daisuke; Palanisamy, Balaji (Georgia Institute of Technology, 2009)
      The storage of health records in electronic format, and the wide-spread sharing of these records among different health care providers, have enormous potential benefits to the U.S. healthcare system. These benefits ...
    • A Power Capping Controller for Multicore Processors 

      Almoosa, Nawaf; Song, William; Wardi, Yorai; Yalamanchili, Sudhakar (Georgia Institute of Technology, 2011)
      This paper presents an online controller for tracking power-budgets in multicore processors using dynamic voltage-frequency scaling. The proposed control law comprises an integral controller whose gain is adjusted online ...
    • Power Modeling for GPU Architecture Using McPAT 

      Lim, Jieun; Lakshminarayana, Nagesh B.; Kim, Hyesoon; Song, William; Yalamanchili, Sudhakar; Sung, Wonyong (Georgia Institute of Technology, 2013)
      Graphics Processing Units (GPUs) are very popular for both graphics and general-purpose applications. Since GPUs operate many processing units and manage multiple levels of memory hierarchy, they consume a significant ...
    • Power- and area-efficient single SISO architecture of Turbo decoder 

      Lee, Dongwon; Wolf, Wayne (Georgia Institute of Technology, 2009)
      In this paper, we propose a power- and area-efficient architecture of Turbo decoder. In order to improve the nonfunctional performance metrics such as power consumption and area, we use the trade-off method between bit ...
    • Redactable Signatures on Data with Dependencies 

      Bauer, David; Blough, Douglas M.; Mohan, Apurva (Georgia Institute of Technology, 2009)
      The storage of personal information by service providers entails a significant risk of privacy loss due to data breaches. One way to mitigate this problem is to limit the amount of personal information that is provided. ...
    • Security Refresh: Prevent Malicious Wear-out and Increase Durability for Phase-Change Memory with Dynamically Randomized Address Mapping 

      Seong, Nak Hee; Woo, Dong Hyuk; Lee, Hsien-Hsin S. (Georgia Institute of Technology, 2009-11)
      Phase-change Random Access Memory (PRAM) is an emerging memory technology for future computing systems. It is nonvolatile and has a faster read latency and potentially higher storage density than other memory alternatives. ...
    • Speculative Execution on Multi-GPU Systems 

      Diamos, Gregory; Yalamanchili, Sudhakar (Georgia Institute of Technology, 2009)
      The lag of parallel programming models and languages behind the advance of heterogeneous many-core processors has left a gap between the computational capability of modern systems and the ability of applications to ...