Now showing items 1-11 of 11

    • Chameleon: Virtualizing Idle Acceleration Cores of A Heterogeneous Multi-Core Processor for Caching and Prefetching 

      Woo, Dong Hyuk; Fryman, Joshua B.; Knies, Allan D.; Lee, Hsien-Hsin Sean (Georgia Institute of Technology, 2008)
      Heterogeneous multi-core processors have emerged as an energy- and area-efficient architectural solution to improving performance for domain-specific applications such as those with a plethora of data-level parallelism. These ...
    • Collective Endorsement and the Dissemination Problem in Malicious Environments 

      Lakshmanan, Subramanian; Manohar, Deepak J.; Ahamad, Mustaque; Venkateswaran, H. (Georgia Institute of Technology, 2004-03-08)
      We consider the problem of disseminating an update known to a set of servers to other servers in the system via a gossip protocol. Some of the servers can exhibit malicious behavior. We require that only the updates ...
    • Compiler Assisted Dynamic Management of Registers for Network Processors 

      Collins, Ryan; Alegre, Fernando; Zhuang, Xiaotong; Pande, Santosh (Georgia Institute of Technology, 2005)
      Modern network processors such as the Intel IXP family hide the latency of slow instructions by supporting multiple threads of execution. Context switches in the IXP architecture are designed to be very fast. However, the ...
    • Creating Efficient Execution Platforms with V(irtualized) Services 

      Seshasayee, Balasubramanian; Schwan, Karsten (Georgia Institute of Technology, 2008)
      Virtualization is creating new opportunities for innovative uses of middleware technologies. In this paper, we present such opportunities for mobile or pervasive environments, where virtualization efforts face challenges ...
    • A Dynamic, Partitioned Global Address Space Model for High Performance Clusters 

      Yalamanchili, Sudhakar; Young, Jeff; Duato, José; Silla, Federico (Georgia Institute of Technology, 2008)
      Memory-to-memory latency is a critical performance determinant of scalable computing systems. The use of modern interconnect fabrics tightly coupled to the processor-memory hierarchy such as AMD’s HyperTransportTM (HT) ...
    • A HyperTransport-Enabled Global Memory Model For Improved Memory Efficiency 

      Young, Jeffrey; Yalamanchili, Sudhakar; Silla, Federico; Duato, José (Georgia Institute of Technology, 2008)
      Modern and emerging data centers are presenting unprecedented demands in terms of cost and energy consumption, far outpacing architectural advances related to economies of scale. Consequently, blade designs exhibit ...
    • Intelligent Cache Management by Exploiting Dynamic UTI/MTI Behavior 

      Fryman, Joshua Bruce; Huneycutt, Chad Marcus; Snyder, Luke Aron; Loh, Gabriel H.; Lee, Hsien-Hsin Sean (Georgia Institute of Technology, 2005)
      This work addresses the problem of the increasing performance disparity between the microprocessor and memory subsystem. Current L1 caches fabricated in deep submicron processes must either shrink to maintain timing, or ...
    • Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design 

      Ekpanyapong, Mongkol; Minz, Jacob Rajkumar; Watewai, Thaisiri; Lee, Hsien-Hsin Sean; Lim, Sung Kyu (Georgia Institute of Technology, 2003)
      As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communication within a single cycle, thus decaying ...
    • Self-Virtualized I/O: High Performance, Scalable I/O Virtualization in Multi-core Systems 

      Raj, Himanshu; Ganev, Ivan Borissov; Schwan, Karsten; Xenidis, Jimi (Georgia Institute of Technology, 2006)
      Virtualizing I/O subsystems and peripheral devices is an integral part of system virtualization. This paper advocates the notion of self-virtualized I/O (S-VIO). Specifically, it proposes a hypervisor-level abstraction ...
    • Virtualization Services: Accelerated I/O Support in Multi-Core Systems 

      Raj, Himanshu; Schwan, Karsten (Georgia Institute of Technology, 2010)
      Virtualization services permit I/O subsystems and peripheral devices to be virtualized by placing select functionality on specialized cores and/or on cores situated ‘closer’ to devices. The approach is used to implement ...
    • A Virtualized Quality of Service Packet Scheduling Accelerator 

      Chuang, Kangtao Kendall; Yalamanchili, Sudhakar; Gavrilovska, Ada; Schwan, Karsten (Georgia Institute of Technology, 2008-05-21)
      This paper introduces the virtualization of a Quality of Service Packet Scheduler. Virtualization in terms of resource sharing among multiple processes of virtual packet schedulers implementing the DWCS algorithm on an ...