• Channel and Pin Assignment for Three Dimensional Packaging Routing 

      Minz, Jacob Rajkumar; Lim, Sung Kyu (Georgia Institute of Technology, 2004-05-24)
      Three dimensional packaging is becoming a popular concept because of the numerous advantages it has to offer over the existing conventional technologies. System on Packages (SOP) is an example of three dimensional packaging. ...
    • Global Routing for Three Dimensional Packaging 

      Minz, Jacob Rajkumar; Lim, Sung Kyu (Georgia Institute of Technology, 2003)
      Three dimensional packaging is becoming a popular concept because of the numerous advantages it has to offer over the existing conventional technologies. System on Packages (SOP) is an example of three dimensional packaging. ...
    • Global Routing Paradigm for System-on-Package 

      Minz, Jacob Rajkumar; Pathak, Mohit; Lim, Sung Kyu (Georgia Institute of Technology, 2003)
      The true potential of three dimensional System-On-Package (SOP) technology lies in its capability to integrate both active and passive components into a single high speed/density multi-layer packaging substrate. We propose ...
    • Layer Assignment for System on Packages 

      Minz, Jacob Rajkumar; Lim, Sung Kyu (Georgia Institute of Technology, 2003)
      The routing environment for the new emerging mixed-signal System-on-Package (SOP) technology is more advanced than that of the conventional PCB or MCM technology - pins are located at all layers of SOP packaging substrate ...
    • Multi-layer Floorplanning for Reliable System-on-Package 

      Shiu, Pun Hang; Lim, Sung Kyu (Georgia Institute of Technology, 2003)
      Physical design automation for the new emerging mixed-signal System-on-Package (SOP) technology requires a new kind of floorplanner--it must place both active components such as digital IC, analog ICs, memory modules, MEMS, ...
    • Physical Layout Automation for System-On-Packages 

      Lim, Sung Kyu (Georgia Institute of Technology, 2003)
      System-On-Package (SOP) paradigm proposes a unified chip-plus-package view of the design process, where heterogeneous system components such as digital ICs, analog/RF ICs, memory, optical interconnects, MEMS, and passive ...