Chameleon: Virtualizing Idle Acceleration Cores of A Heterogeneous Multi-Core Processor for Caching and Prefetching

Show full item record

Please use this identifier to cite or link to this item: http://hdl.handle.net/1853/27232

Title: Chameleon: Virtualizing Idle Acceleration Cores of A Heterogeneous Multi-Core Processor for Caching and Prefetching
Author: Woo, Dong Hyuk ; Fryman, Joshua B. ; Knies, Allan D. ; Lee, Hsien-Hsin Sean
Abstract: Heterogeneous multi-core processors have emerged as an energy- and area-efficient architectural solution to improving performance for domain-specific applications such as those with a plethora of data-level parallelism. These processors typically contain a large number of small, compute-centric cores for acceleration while keeping one or two high-performance ILP cores on the die to guarantee single-thread performance. Although a major portion of the transistors are occupied by the acceleration cores, these resources will sit idle when running unparallelized legacy codes or the sequential parts of an application. To address this under-utilization issue, in this paper, we introduce Chameleon, a flexible heterogeneous multi-core architecture to virtualize these resources for enhancing memory performance when running sequential programs. The Chameleon architecture can dynamically virtualize the idle acceleration cores into a last-level cache, a data prefetcher, or a hybrid between these two techniques. In addition, Chameleon can operate in an adaptive mode which dynamically configures the acceleration cores between the hybrid mode and the prefetch-only mode by monitoring the effectiveness of Chameleon caching scheme. In our evaluation using SPEC2006 benchmark suite, different levels of performance improvements were achieved in different modes for different applications. In the case of the adaptive mode, Chameleon improves the performance of SPECint06 and SPECfp06 by 33% and 22% on average. When considering only memory-intensive applications, Chameleon improves the system performance by 53% and 33%.
Type: Technical Report
URI: http://hdl.handle.net/1853/27232
Date: 2008
Contributor: Georgia Institute of Technology. School of Electrical and Computer Engineering
Intel Corporation. Microprocessor Technology Labs
Intel Research Berkeley
Relation: CERCS ; GIT-CERCS-08-11
Publisher: Georgia Institute of Technology
Subject: Cache design
Caching
Computer architecture
Cores
Latency
Multi-core processor
Prefetcher
Programming

All materials in SMARTech are protected under U.S. Copyright Law and all rights are reserved, unless otherwise specifically indicated on or in the materials.

Files in this item

Files Size Format View
git-cercs-08-11.pdf 677.7Kb PDF View/ Open

This item appears in the following Collection(s)

Show full item record