All-copper chip-to-substrate interconnects for high performance integrated circuit devices

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Please use this identifier to cite or link to this item: http://hdl.handle.net/1853/28211

Title: All-copper chip-to-substrate interconnects for high performance integrated circuit devices
Author: Osborn, Tyler Nathaniel
Abstract: In this work, all-copper connections between silicon microchips and substrates are developed. The semiconductor industry advances the transistor density on a microchip based on the roadmap set by Moore's Law. Communicating with a microprocessor which has nearly one billion transistors is a daunting challenge. Interconnects from the chip to the system (i.e. memory, graphics, drives, power supply) are rapidly growing in number and becoming a serious concern. Specifically, the solder ball connections that are formed between the chip itself and the package are challenging to make and still have acceptable electrical and mechanical performance. These connections are being required to increase in number, increase in power current density, and increase in off-chip operating frequency. Many of the challenges with using solder connections are limiting these areas. In order to advance beyond the limitations of solder for electrical and mechanical performance, a novel approach to creating all-copper connections from the chip-to-substrate has been developed. The development included characterizing the electroless plating and annealing process used to create the connections, designing these connections to be compatible with the stress requirements for fragile low-k devices, and finally by improving the plating/annealing process to become process time competitive with solder. It was found that using a commercially available electroless copper bath for the plating, followed by annealing at 180 C for 1 hour, the shear strength of the copper-copper bond was approximately 165 MPa. This work resulted in many significant conclusions about the mechanism for bonding in the all-copper process and the significance of materials and geometry on the mechanical design for these connections.
Type: Dissertation
URI: http://hdl.handle.net/1853/28211
Date: 2009-04-02
Publisher: Georgia Institute of Technology
Subject: Microelectronic packaging
Interconnects
Electroless copper
Plating
Electrodeposition
Interconnects (Integrated circuit technology)
Copper
Department: Chemical Engineering
Advisor: Committee Chair: Kohl, Paul; Committee Member: Bidstrup Allen, Sue Ann; Committee Member: Fuller, Thomas; Committee Member: Hesketh, Peter; Committee Member: Hess, Dennis; Committee Member: Meindl, James
Degree: Ph.D.

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