SoftCache Architecture

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Please use this identifier to cite or link to this item: http://hdl.handle.net/1853/7205

Title: SoftCache Architecture
Author: Fryman, Joshua Bruce
Abstract: Multiple trends in computer architecture are beginning to collide as process technology reaches ever smaller feature sizes. Problems with managing power, access times across a die, and increasing complexity to sustain growth are now blocking commercial products like the Pentium 4. These problems also occur in the embedded system space, albeit in a slightly different form. However, as process technology marches on, today's high-performance space is becoming tomorrow's embedded space. New techniques are needed to overcome these problems. In this thesis, we propose a novel architecture called SoftCache to address these emerging issues for embedded systems. We reduce the on-die memory controller infrastructure which reduces both power and space requirements, using the ubiquitous network device arena as a proving ground of viability. In addition, the SoftCache achieves further power and area savings by converting on-die cache structures into directly addressable SRAM and reducing or eliminating the external DRAM. To avoid the burden of programming complexity this approach presents to the application developer, we provide a transparent client-server dynamic binary translation system that runs arbitrary ELF executables on a stripped-down embedded target. One drawback to such a scheme lies in the overhead of additional instructions required to effect cache behavior, particularly with respect to data caching. Another drawback is the power use when fetching from remote memory over the network. The SoftCache comprises a dynamic client-server translation system on simplified hardware, targeted at Intel XScale client devices controlled from servers over the network. Reliance upon a network server as a ``backing store' introduces new levels of complexity, yet also allows for more efficient use of local space. The explicitly software managed aspects create a cache of variable line size, full associativity, and high flexibility. This thesis explores these particular issues, while approaching everything from the perspective of feasibility and actual architectural changes.
Type: Dissertation
URI: http://hdl.handle.net/1853/7205
Date: 2005-07-19
Publisher: Georgia Institute of Technology
Subject: Low-power
Computer architecture
Embedded systems
Cache design
Sensor networks
Department: Computing
Advisor: Committee Co-Chair: Lee, Hsien-Hsin Sean; Committee Co-Chair: Ramachandran, Kishore; Committee Member: Mackenzie, Kenneth; Committee Member: Pande, Santosh; Committee Member: Schimmel, David; Committee Member: Schwan, Karsten
Degree: Ph.D.

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